Tags : Browse Projects

Select a tag to browse associated projects and drill deeper into the tag cloud.

Tiny C Compiler

Compare

  Analyzed 4 months ago

TinyCC (aka TCC) is a small but hyper fast C compiler. Unlike other C compilers, it is meant to be self-sufficient: you do not need an external assembler or linker because TCC does that for you. TCC compiles so fast that even for big projects Makefiles may not be necessary. TCC not only supports ... [More] ANSI C, but also most of the ISO C99 and ISO C11 standard and also many GNUC extensions. TCC can also be used to make C scripts, i.e. pieces of C source that you run as a script. Compilation is so fast that your script will be as fast as if it was an executable. TCC can also automatically generate memory and bound checks while allowing all C pointers operations. With libtcc, you can use TCC as a backend for dynamic code generation. [Less]

103K lines of code

28 current contributors

almost 2 years since last commit

7 users on Open Hub

Activity Not Available
4.0
   
I Use This

NEORV32

Compare

  Analyzed 4 months ago

A size-optimized, customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.

44.6K lines of code

0 current contributors

5 months since last commit

1 users on Open Hub

Activity Not Available
0.0
 
I Use This
Licenses: No declared licenses
Tags risc_v

meta-riscv

Compare

  Analyzed 4 months ago

OpenEmbedded/Yocto layer for RISC-V Architecture

146 lines of code

0 current contributors

6 months since last commit

1 users on Open Hub

Activity Not Available
0.0
 
I Use This

serv

Compare

  Analyzed 4 months ago

SERV - The SErial RISC-V CPU

6.4K lines of code

6 current contributors

5 months since last commit

1 users on Open Hub

Activity Not Available
0.0
 
I Use This
Licenses: No declared licenses
Tags risc_v

PULP Platform

Compare

  Analyzed 4 months ago

An open-source microcontroller system based on RISC-V

2.69M lines of code

64 current contributors

5 months since last commit

0 users on Open Hub

Activity Not Available
0.0
 
I Use This
Licenses: No declared licenses
Tags risc_v

RISC-V BOOM

Compare

  Analyzed 4 months ago

Berkeley Out-of-Order Machine, a out of order CPU based on the risc-v instruction set architecture.

30.1K lines of code

14 current contributors

5 months since last commit

0 users on Open Hub

Activity Not Available
0.0
 
I Use This
Licenses: No declared licenses

Rocket-Chip

Compare

  Analyzed 4 months ago

Rocket Chip is Berkeley's RISC-V based SOC generator. The open-source release is capable of generating a multi-core system with Rocket scalar cores, Z-Scale control processors, and a coherent memory system.

45.4K lines of code

41 current contributors

5 months since last commit

0 users on Open Hub

Activity Not Available
0.0
 
I Use This
Licenses: No declared licenses

SHAKTI

Compare

  Analyzed 4 months ago

IIT Madras Shakti Open Source Processor family - based on the RISCV ISA

401K lines of code

8 current contributors

over 5 years since last commit

0 users on Open Hub

Activity Not Available
0.0
 
I Use This
Licenses: No declared licenses
Tags cpu risc_v

ReonV

Compare

  Analyzed 4 months ago

ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 architecture, now changed to RISC-V ISA.

473K lines of code

0 current contributors

over 2 years since last commit

0 users on Open Hub

Activity Not Available
0.0
 
I Use This
Licenses: No declared licenses

VexRiscv

Compare

  Analyzed 4 months ago

A FPGA friendly 32 bit RISC-V CPU implementation

87.6K lines of code

8 current contributors

5 months since last commit

0 users on Open Hub

Activity Not Available
0.0
 
I Use This
Licenses: No declared licenses
Tags cpu risc_v