Project Summary
Verilator converts synthesizable Verilog HDL modules into SystemC modules. This enables users with Verilog code to have a publicly available co-simulation environment. For all information, see http://www.veripool.com/verilator.html.
In a Nutshell, Verilator...
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has a well established, mature codebase
maintained by a very large development team
with increasing Y-O-Y commits -
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took an estimated 1 years of effort (COCOMO model)
starting with its first commit in August, 2006
ending with its most recent commit 2 months ago
Quick Reference
Artistic License 2.0
Permitted
Commercial Use
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Sub-License
Private Use
Forbidden
Hold Liable
Use Trademarks
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Include Copyright
State Changes
Include Install Instructions
Rename
These details are provided for information only. No information here is legal advice and should not be used as such.
GNU Lesser General Public License v3.0 only
Permitted
Commercial Use
Modify
Distribute
Place Warranty
Use Patent Claims
Forbidden
Sub-License
Hold Liable
Required
Distribute Original
Disclose Source
Include Copyright
State Changes
Include License
Include Install Instructions
These details are provided for information only. No information here is legal advice and should not be used as such.
Project Security
Vulnerabilities per Version ( last 10 releases )
There are no reported vulnerabilities
Project Vulnerability Report
Security Confidence Index
Vulnerability Exposure Index
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30 Day SummaryJan 1 2025 — Jan 31 2025
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12 Month SummaryJan 31 2024 — Jan 31 2025
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