The aim of the FPGALink project is to provide a hardware abstraction layer for hardware involving an FPGA connected to a computer over USB, to abstract core functionality like FPGA-programming and subsequent host-FPGA communication. It doesn't matter whether the hardware uses an AVR, an FX2LP or an ARM-based micro for its USB interface. It doesn't matter whether the FPGA is from Xilinx or Altera or Lattice or whomever. It doesn't matter whether the interface between them is a fast 43MiB/s parallel synchronous interface, a much slower EPP interface or some sort of USART connection. The cross-platform, cross-language host-side API is the same, and the FPGA-side (VHDL or Verilog) FIFO interface is the same, so you can easily port your design to a new FPGA devkit or to your own custom PCB.
Commercial Use
Modify
Distribute
Place Warranty
Sub-License
Hold Liable
Distribute Original
Disclose Source
Include Copyright
State Changes
Include License
These details are provided for information only. No information here is legal advice and should not be used as such.
Commercial Use
Modify
Distribute
Place Warranty
Use Patent Claims
Sub-License
Hold Liable
Distribute Original
Disclose Source
Include Copyright
State Changes
Include License
Include Install Instructions
These details are provided for information only. No information here is legal advice and should not be used as such.
Commercial Use
Modify
Distribute
Place Warranty
Use Patent Claims
Sub-License
Hold Liable
Distribute Original
Disclose Source
Include Copyright
State Changes
Include License
Include Install Instructions
These details are provided for information only. No information here is legal advice and should not be used as such.
There are no reported vulnerabilities
30 Day SummaryDec 21 2023 — Jan 20 2024
|
12 Month SummaryJan 20 2023 — Jan 20 2024
|