Analyzed
4 days
ago.
based on code collected
about 1 month
ago.
Project Summary
Connectal makes it easy to develop hardware-accelerated software using FPGAs.
Define the hardware/software interface, write the HDL, write the software, build it and test it. No drivers required!
Connectal currently supports Xilinx Virtex, Kintex, and especially Zynq FPGAs as well as Altera FPGAs.
We develop our hardware using Bluespec System Verilog.
In a Nutshell, connectal...
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took an estimated 18 years of effort (COCOMO model)
starting with its first commit in November, 2012
ending with its most recent commit over 1 year ago
Quick Reference
MIT License
Permitted
Commercial Use
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Sub-License
Private Use
Forbidden
Hold Liable
Required
Include Copyright
Include License
These details are provided for information only. No information here is legal advice and should not be used as such.
Project Security
Vulnerabilities per Version ( last 10 releases )
There are no reported vulnerabilities
Project Vulnerability Report
Security Confidence Index
Poor security track-record
Favorable security track-record
Vulnerability Exposure Index
Many reported vulnerabilities
Few reported vulnerabilities
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30 Day SummaryJan 1 2025 — Jan 31 2025
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12 Month SummaryJan 31 2024 — Jan 31 2025
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