Managed Projects

GHDL

  Analyzed about 1 month ago

GHDL is an open-source analyzer, compiler, simulator and (experimental) synthesizer for VHDL, a Hardware Description Language (HDL). GHDL provides full support for the 1987, 1993, 2002 versions of the IEEE 1076 VHDL standard, and partial for the 2008 revision. GHDL allows you to analyse and ... [More] elaborate sources for generating machine code from your design. [Less]

900K lines of code

18 current contributors

2 months since last commit

10 users on Open Hub

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4.66667
   
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Electronic Design Automation Abstraction (EDA²)

  Analyzed about 1 month ago

26.9K lines of code

0 current contributors

4 months since last commit

2 users on Open Hub

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0.0
 
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Licenses: No declared licenses

[DUPLICATE] MINGW-packages

  Analyzed about 1 month ago

Package scripts for MinGW-w64 targets to build under MSYS2.

3.92K lines of code

101 current contributors

3 months since last commit

2 users on Open Hub

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5.0
 
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Tags packages

pyVHDLModel

  Analyzed about 1 month ago

An abstract language model of VHDL written in Python.

6.95K lines of code

0 current contributors

5 months since last commit

2 users on Open Hub

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5.0
 
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Hardware Description Languages

  Analyzed about 1 month ago

Resources for open source electronic design automation (EDA), focused on using Hardware Description Languages targeting FPGA (but not only).

18.4K lines of code

0 current contributors

2 months since last commit

1 users on Open Hub

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0.0
 
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pyTooling

  Analyzed about 1 month ago

pyTooling is a collection of arbitrary useful classes, decorators, meta-classes and exceptions.

26K lines of code

0 current contributors

3 months since last commit

1 users on Open Hub

Activity Not Available
0.0
 
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Licenses: No declared licenses

F4PGA

  Analyzed about 1 month ago

610K lines of code

0 current contributors

3 months since last commit

1 users on Open Hub

Activity Not Available
0.0
 
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