PulseView

We're happy to announce that libsigrok now supports the Saleae Logic16 logic analyzer. This is the successor product of the well-known Saleae Logic (an 8-channel logic analyzer with a max. samplerate of 24MHz and streaming capabilities). The ... [More] Logic16 has 16 channels and can sample at rates of up to 100MHz, depending on the number of channels used. If you only need 3 channels you can sample at 100MHz, or 50MHz for 6 channels, or 32MHz for 9 channels, or 16MHz when using all 16 channels. The property of the Logic16 that makes it really interesting is that it can still stream out the data live over USB (like the Logic) and is thus not limited to any internal buffer size of the logic analyzer itself, while at the same time allowing a samplerate higher than 24MHz. This makes it possible to capture fast signals for longer periods of time (as opposed to just a few milliseconds as is the case for many other devices) which can be very useful in practice. It also has the advantage that you can switch between two different voltage threshold settings, allowing you to debug either 1.8V / 3.3V systems, or 5V systems. Of course it still has the same limitations as the Logic, too. Whether the continuous byte stream from the Logic16 can be received quickly enough over USB without missing any bytes depends on various random factors, such as the USB controller in your PC, the OS/kernel version used, the amount of other USB devices connected and how much data those transfer at the same time, etc. etc. But still, for many cases it works well enough to make it quite useful. Many thanks to Marcus Comstedt for figuring out how the Logic16 protocol works, and for writing the libsigrok driver! He also documented the protocol in the wiki, as well as various firmware internals. We also have some teardown photos, pinouts of the ICs used in the Logic16 and their connections, EEPROM layout and other info in the wiki, if you're interested in this kind of stuff. The device uses a Cypress FX2 USB chip and a Xilinx Spartan-3A XC3S200A FPGA internally. The first needs a firmware upload when the Logic16 is attached to USB, the latter needs an FPGA bitstream upload upon USB connection (as well as another bitstream upload whenever the voltage threshold setting is changed). Thanks to Marcus Comstedt again who provided the sigrok-fwextract-saleae-logic16 tool which you can use to extract the FX2 firmware and the two FPGA bitstreams from the vendor software. See the manpage for details.   [Less]

The collectd project is the de facto standard setup for server statistics: it grabs all kinds of local statistics (network counters, disk I/O, etc) and logs it locally or to a remote collectd, say on a dedicated statistics machine. It's a very ... [More] modular system: everything is in plugins, including input sources like SNMP and OneWire. The default output plugin is the venerable RRDtool. This stores values and averages them over time, and creates graphs on demand. Collectd has just released version 5.4, now with a sigrok plugin. That means any device which can be accessed via libsigrok can feed information to collectd, for storage and graphing with RRDtool or any other output plugin. This is intended for the many analog devices supported in libsigrok, not the oscilloscopes and logic analyzers of course. These graphs were made using a CEM DT-8852 sound level meter and UNI-T UT325 thermometer:   These show my clunky old air conditioning unit adding a whopping 19 dB(A) to the noise level, and the effect that has on the temperature. I also watched a very loud movie with lots of explosions in the evening! Here's the collectd configuration that generated the above: LoadPlugin "sigrok" <Plugin "sigrok"> LogLevel 3 <Device "Sound level"> Driver "cem-dt-885x" conn "/dev/ttyUSB3" MinimumInterval 1 </Device> <Device "Temperature"> Driver "uni-t-ut32x" conn "1a86.e008" MinimumInterval 1 </Device> </Plugin> What's obviously missing from the above is a measurement of the power usage of that air conditioning unit. I'm not sure I want to know... [Less]

Hi everyone! We're happy to announce the new libsigrok 0.2.1 release. This is mostly a bugfix release with a few additional new drivers to support more hardware. No major API changes were performed. We added support for two new logic analyzers. ... [More] One of them is the IKALOGIC Scanalogic-2, a 4-channel device with a max. samplerate of 20MHz. The driver was contributed by Marc Schink (thanks a lot!), who also wrote up some nice documentation about the USB HID based protocol in the wiki. The other device we now support is also an IKALOGIC device (just a coincidence), namely the new ScanaPLUS, a 9-channel logic analyzer with a fixed samplerate of 100MHz, which compresses the captured data and streams it to the PC. This device uses an FPGA internally and an FTDI FT232H for data transfers. The protocol is thus not USB HID based like on the Scanalogic-2. We documented the ScanaPLUS USB protocol in the wiki too, if you want to have a look at the details. We now also support two additional sound level meters, the CEM DT-8852 and the Kecheng KC-330B. Please check the previous blog post about these devices. Finally, support for four new multimeters has been added, the UNI-T UT60A and UNI-T UT60E (thanks Florian Knodt!), the Voltcraft M-3650D (thanks Florian Steinhardt!) and the Voltcraft VC-830. They were all pretty easy to add to our generic 'serial-dmm' driver which can support a wide variety of serial-based DMMs with "simple" protocol. Apart from that we added a few new config keys, config info types, and error codes. We also did the usual bunch of code cleanups, documentation improvements, and bugfixes. Please read the NEWS file for details. You can download the libsigrok-0.2.1.tar.gz tarball from sigrok.org/download as usual. Have fun!   [Less]

We now have support for two more sound level meters in libsigrok. Both can do live streaming, and do standalone logging for later retrieval. First is the CEM DT-8852, a large handheld unit. It has all the usual features you'd expect in a sound level ... [More] meter, and claims IEC 61672-1 Class 2 compliance. Particularly interesting is the fact that it can stream its dB measurements to the host at 20Hz; this sort of device generally streams at 1 or 2Hz. The firmware is somewhat... temperamental. It was a particular challenge getting the driver to control settings on the device. The vendor software typically takes between 0.1 and 10 seconds before changing a setting actually takes effect on the hardware. The sigrok driver does considerably better: it's reliably under 1.5 seconds, and usually much faster. It all works very well now: the sigrok driver has workarounds for all known bugs. The second new SLM driver is for the Kecheng KC-330B. It has a "USB stick" form factor, and so is intended mostly for standalone logging. It doesn't work very well: logging can only be started manually, by pressing the button, and even then it's not so sure to actually work. The sigrok driver only supports streaming from this device for that reason: the data logging functionality on the device is just too unreliable. [Less]

We're happy to announce that libsigrok now supports the Ikalogic SCANALOGIC-2 logic analyzer. This is a low-cost 4-channel logic analyzer with a max. samplerate of 20MHz with 256Ksamples of memory per channel. It is available both as a fully ... [More] assembled, ready-to-use device, as well as a slightly cheaper DIY kit where you can solder most of the parts on your own. Many thanks to Marc Schink for contributing the driver and documenting the USB protocol of the logic analyzer in the wiki!   [Less]

It's been a while since we last released a new version of libsigrok. A lot of work has gone into the library since then, but we somehow never got around to doing releases — there was always some major API change coming, or a driver that was nearly ... [More] finished. So here's a release now, and it's a good one. We're simultaneously releasing the following: libsigrok 0.2.0 libsigrokdecode 0.2.0 sigrok-cli 0.4.0 PulseView 0.1.0 As announced earlier, libsigrok now supports analog sources, such as oscilloscopes. But this has actually led to many other classes of hardware as well, and we wrote tons of drivers. We've added support for the following: Logic Analyzers CWAV USBee DX ZEROPLUS LAP-16128U Oscilloscopes Hantek DSO-2090 Rigol DS1052D, DS1052E, DS1102D, DS1102E Multimeters Agilent U1231A, U1232A, U1233A Brymen BM857 Digitek DT4000ZC/TekPower TP4000ZC Fluke 187, 189, 287, 289 and the Scopemeter 199B Mastech MAS345 Metex ME-31, M-3640D PCE PCE-DM32 PeakTech 3410, 4370 RadioShack 22-168, 22-805, 22-812 Tecpel DMM-8060, DMM-8061 UNI-T UT61D, UT61E V&A VA18B Victor 70C, 86C Voltcraft VC-820, VC-840 Sound level meters Colead SL-5868P Tondaj SL-814 Temperature, humidity and CO loggers Lascar EL-USB (various models) MIC 98581, 98583 All of these devices have their own page in our wiki, with full teardowns and protocol documentation. You can find an overview here. Existing drivers have seen many bugfixes and improvements as well: check the NEWS file for details. There are also input modules for the VCD and WAV file formats, and an output module that pretty-prints analog output with appropriate units. The commandline client, sigrok-cli, has been updated to deal with the analog devices, and has had an overhaul of the commandline options; this should make it a bit more intuitive to use. Check the man page for details and some examples. The python decoder library, libsigrokdecode, now exposes decoder options to clients. There is also a new decoder for the Dallas DS1307 RTC chip's protocol. Up until now, sigrok-cli has been the only officially supported sigrok client. That's changing: we're happy to announce that PulseView is getting its first release as well, and will be officially supported from now on. That means releases of libsigrok and pulseview will be kept in sync, with respect to API/ABI compatibility. We also enforce this in the git development repository. When PulseView gets support for protocol decoding, we'll keep it in sync with libsigrokdecode as well. All four releases are considered pretty stable; we don't know of anything that crashes at the moment. If you find a bug, please take the time to post a bug report.     [Less]

After a year of effort, PulseView - sigrok's new logic analyzer, oscilloscope and MSO GUI - is nearly ready for its debut release: v0.1.0. At this stage we're making a concerted effort to drive up the quality of our release candidate by giving it a ... [More] thorough round of bug hunting and bug fixing. The range of features offered by PulseView at this stage is quite modest, but those features that it does offer should work well, without crashing of malfunctioning. In order to experience the joy, or indeed pain, that our users may experience, I've started trying to use PulseView to solve a real problem. This is not the first time I've attempted this task; I've tried to do it several times before, but it hasn't been possible until now to get through this without some kind of crash or error. The Problem Cypress FX2 based logic analysers have been supported by our fx2lafw open firmware for some time now. Most of these devices are very simple having only a single FX2 on the board. There is a slightly more interesting device: the USBee AX, which has an ADC attached to the upper 8-bits of the FX2's data input. It is therefore a very simple mixed signal device. I acquired a chinese clone of this device about a year ago: the EE Electronics ESLA201A. For a while now, I've been working on a branch to add support for these MSO devices both to the fx2lafw firmware and the libsigrok driver. The results so far have been mixed (no pun intended). While the device seems to do a reasonable job of capturing signals from an NE555 board that I have, when I connect the analog input to ground, it goes crazy: This trace was taken with the analog input grounded, and capturing at 1MHz. Pretty broken. Yo dawg! I heard you like Logic Analysers... So why is the capture getting corrupted? Fortunately (courtesy of Bert Vermeulen), I have just the tool to find out: The OpenBench Logic Sniffer. This device is a logic analyser capable of sampling at up to 200MHz - fast enough to trace the ESLA201A while it samples. Here I have attached 8 probes to the 8 data output lines of the ESLA201A's TLC5510I ADC, and a probe to the ADC clock input. I then set the ESLA201A to sample continuously with sigrok-cli. I like to use cpipe to measure that the pipe throughput is what I would expect it to be, and then dump the data in /dev/null. $ sigrok-cli --driver=fx2lafw --device samplerate=1M --continuous -O binary | cpipe -vt > /dev/null thru: 1854.344ms at   69.0kB/s (  69.0kB/s avg)  128.0kB thru: 132.646ms at  965.0kB/s ( 128.8kB/s avg)  256.0kB thru: 127.458ms at 1004.3kB/s ( 181.6kB/s avg)  384.0kB thru: 132.681ms at  964.7kB/s ( 227.8kB/s avg)  512.0kB thru: 127.580ms at 1003.3kB/s ( 269.5kB/s avg)  640.0kB thru: 132.563ms at  965.6kB/s ( 306.3kB/s avg)  768.0kB thru: 132.689ms at  964.7kB/s ( 339.4kB/s avg)  896.0kB ...then I set PulseView to capture a trace: So far this is what I would expect to see. Channel 0 is the clock input, and channels 1-8 are the data output, where channel 8 is the MSB. Therefore the ADC is reading a value of 127, which for a 0V input is correct. So could this be an issue of timing? The TLC5510I has a minimum high and low clock pulse duration of 25ns. To find out, we will use PulseView's cursors feature. Putting the cursors around the trough, we can measure a low-duration of 40ns. So no problem there. There are no other constraints on the timing signal - they don't have to be symetrical pulses. So I kept repeatedly clicking Run to see if things would always run so smoothly. Suddenly this happened... Lulwat? The ADC seems to be having some kind of spaz-attack. So far I havn't been able to figure out exactly what has caused this. However, there do occasionally seem to be problems with the clocks signal: If this logic analyser is seeing the what the ADC is seeing, this would explain a lot about why the ADC has gone crazy. The question to determine whether this is a problem with the fx2lafw firmware, or whether there is some signal integrity - and what would cause that. By way of comparison, I decided to see how the USBee software suite would fair on the same problem. So I fired up my trusty Windows XP VM. Interestingly, it too exhibited a very similar behaviour. I hadn't done any logic analysis with the official firmware before, so I wasn't sure if it would show some mistake I had made in the shape of my clock pulse. In the end it showed a clock signal that was almost identical - except the low-pulses were 30ns rather than 40ns. Conclusion I suspect even if I figure out the cause of the corruption, the device will never be a very good oscilloscope, if it has these kinds of ground bounce effects. This is the decay you can see in the analog trace above, and if there are issues with the design either on the digital or analog side, there may not be much I can do about them. Having said that, even if the board does have digital signalling issues, attaching lots of logic analyser wires to it will make them much worse, so some of the issues we are observing here may have been self induced. Any suggestions would be welcome. But anyway, this is all beside the point. PulseView managed to come through this experiment without crashing and delivered some interesting insights. [Less]

We're happy to announce the 0.1.1 release of sigrok-firmware-fx2lafw, the open-source firmware which allows you to use almost any device with a Cypress FX2/FX2LP chip as a simple logic analyzer (together with libsigrok and a frontend, of course). You ... [More] can download the source tarball from SourceForge as usual. Additionally, you can also grab pre-built firmware files instead, if you don't want to compile them yourself. This is mostly a bugfix release. It features a simpler and more common "./configure && make && make install" build system, updated documentation, and some fixes for differently named sdcc tools on different OSes or distros (e.g. Mac OS X, Fedora, others). It also adds support for the USBee DX device (only logic analyzer functionality, as with the other devices), and support for the older FX2 (not FX2LP) variant of the Cypress USB chip. This is important since we've seen both these cases in practice: older logic analyzers which have the FX2 chip, as well as devices which pretend to have an FX2LP chip but in reality it is a "rebadged" FX2. See the NEWS file for the full list of user-visible changes.   [Less]

We're happy to announce the new libsigrokdecode 0.1.1 release! You can download the source tarball from SourceForge, as usual. This is mostly a bugfix-release, the C library API was not changed. This means existing frontends that work with / are ... [More] linked against libsigrokdecode 0.1.0 (e.g. sigrok-cli 0.3.1) will continue to work just fine, without requiring relinking or recompiling. However, some of the protocol decoders' output changed in ways which are not compatible with the state of the decoders in the last libsigrokdecode release. This means, if you're using any scripts to parse sigrok-cli decoder output, or if you have any "private" protocol decoders that stack on top of one of those shipped with libsigrokdecode, you will have to do some adaptations. You're also encouraged to submit such decoders to be included in libsigrokdecode proper, of course! In addition to all kinds of improvements and bugfixes in existing protocol decoders (PDs), you're probably most interested in what new protocol decoders are now supported. So here's the list: avr_isp: AVR In-System Programming can: Controller Area Network jtag: Joint Test Action Group (IEEE 1149.1) jtag_stm32: Joint Test Action Group / ST STM32 lm75: National LM75 lpc: Low-Pin-Count maxim_ds28ea00: Maxim DS28EA00 1-Wire digital thermometer onewire_link: 1-Wire serial communication bus (link layer) onewire_network: 1-Wire serial communication bus (network layer) sdcard_spi: Secure Digital card (SPI mode) tlc5620: Texas Instruments TLC5620 DAC uart_dump: UART dump This adds up to currently 29 supported PDs. The decoders are in various stages of "feature completeness", of course. Additional improvements and more verbose/complete decoding functionality will be added over time. You can use some example files we've collected in the sigrok-dumps repository to test the protocol decoders. For example, the CAN decoder: $ sigrok-cli -i mcp2515dm-bm-1mbits_msg_222_5bytes.sr -a can:can_rx=2 can: "Start of frame" "SOF" can: "ID: 0 (0x0)" can: "IDE: standard frame" can: "RB0: 0" can: "RTR: data frame" can: "Stuff bit: 1" can: "DLC: 7" can: "Stuff bit: 0" can: "Stuff bit: 1" can: "Stuff bit: 0" can: "Data byte 0: 0xf0" can: "Data byte 1: 0x00" [...] Or, the basic JTAG decoder: $ sigrok-cli -i olimex_stm32-h103_irscan_drscan.sr -a jtag:trst=0:tdi=1:tms=2:tck=3:tdo=4 jtag: "New state: SELECT-DR-SCAN" jtag: "New state: SELECT-IR-SCAN" jtag: "New state: CAPTURE-IR" jtag: "New state: SHIFT-IR" [...] jtag: "New state: SHIFT-IR" jtag: "New state: EXIT1-IR" jtag: "IR TDI: 11111110 (0xfe), 8 bits" jtag: "IR TDO: 11110001 (0xf1), 8 bits" jtag: "New state: UPDATE-IR" Or, stacking the STM32-specific JTAG protocol decoder on top of the JTAG decoder: $ sigrok-cli -i olimex_stm32-h103_irscan_drscan.sr \ -a jtag:trst=0:tdi=1:tms=2:tck=3:tdo=4,jtag_stm32 -s jtag,jtag_stm32 jtag_stm32: "IR: IDCODE" jtag_stm32: "IDCODE: 0x3ba00477 (ver=0x3, part=0xba00, manuf=0x23b, res=0x1)" If you want to contribute any additional sample files for various protocols (*.sr format as produced by sigrok-cli) for our sigrok-dumps repository that would be great! We're also currently in the process of adding a wiki page for every protocol decoder, with detailed information about the protocol it decodes, the decoder implementation and its status, how to use it, which decoders it stacks on (or which ones can stack on top of it), and so on. Check the pages for mx25lxx05d, dcf77, or nunchuk, for some (work in progress) examples. Please check the libsigrokdecode NEWS file for the full list of user-visible changes in this release. As always, we're happy about bug reports, feature suggestions, comments about which protocol decoders you'd want supported next, or even better — patches :)   [Less]

Same as last year, we will be at the Chaos Communication Congress (29c3), this time in Hamburg, Germany. The conference takes place from December 27th to 30th, 2012. We'll have a sigrok "assembly", likely in area 3b of the conference building, where ... [More] we'll be hanging around, working on new sigrok features, new hardware drivers, new protocol decoders and various other things. We'll have lots of gear with us for demo and development purposes, including logic analyzers, oscilloscopes, MSOs, multimeters, and lots more. Bring your own device if you own models we don't yet support or know about. We'll be happy to have a look! Chat with us, give us your suggestions which features you'd like to see, which devices you want to be supported, which protocol decoders you'd like to have, or even help us write some drivers/decoders! Hope to see you there!   [Less]