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Commits : Listings

Analyzed 12 days ago. based on code collected 13 days ago.
Jan 29, 2024 — Jan 29, 2025
Commit Message Contributor Files Modified Lines Added Lines Removed Code Location Date
Updated to new PoC version incl. submodule commits. More... over 9 years ago
Fixed linking in README. More... over 9 years ago
Merge branch 'DE4' More... over 9 years ago
PauloBlaze is now working on the DE4 board. More... over 9 years ago
Updated README. More... over 9 years ago
Merge branch 'DE4' More... over 9 years ago
Added missing Quartus files. More... over 9 years ago
Merge branch 'DE4' More... over 9 years ago
Updated example to comply with PoC (Quartus work around). Added switches to distinguish between Xilinx and Altera synthesis. More... over 9 years ago
Added files for an Altera Stratix IV design on a Terasic DE4 board. More... over 9 years ago
Updated to new PoC version. More... over 9 years ago
Submodule commit. More... over 9 years ago
updated to the new std_logic_vector interface of the pauloBlaze More... over 9 years ago
Added PauloBlaze test project. More... over 9 years ago
Example design now works with PoC's UART modules. More... over 9 years ago
Added new git submodule: pauloBlaze into lib/pauloBlaze More... over 9 years ago
Removed PoC.my_project file from repo -> it's a private file. More... over 9 years ago
Submodule commits. More... over 9 years ago
Merged branch 'Atlys' into 'master' Conflicts: ChipScope/ExampleDesign/ExampleDesign.cpj More... over 9 years ago
Added a reset button. More... over 9 years ago
Added missing clocking constraints. Hardened design for 100 MHz on Spartan-6. Imported cdc file and tok files into ChipScope project. More... over 9 years ago
Merged branch 'Atlys' into 'master' More... over 9 years ago
The example is booting. More... over 9 years ago
First commit for the Atlys example design. More... over 9 years ago
Added git submodules. More... over 9 years ago
Initial commit. More... over 9 years ago